issue compiling modules with SV Interface ports

[unfrostedpoptart]

Hi all.

This has been giving me headaches as I start using SV Interfaces.
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.

Does anyone have an easy solution to this? I could write a dummy
wrapper module, but I do this on dozens of different files, and that
starts becoming a lot of work. I thought of some PERL script to
automatically create this wrapper, but I'm not the best PERL
programmer, so it would take me a long time to get it working.

Thanks for any solutions / suggestions,

David

[Jonathan Bromley]

Post by unfrostedpoptart
This has been giving me headaches as I start using SV Interfaces.
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.
Does anyone have an easy solution to this?

By default, VCS does compilation and elaboration in a
single step (the "vcs" command). In Cadence and Mentor
simulators, you can run an independent compilation step
(ncvlog, vlog) that syntax-checks the module(s) but does
not attempt to do elaboration. I believe the same thing
can be done in VCS, and I *think* the command is "vlogan",
but you'll need to check the docs yourself.

Beware that this sort of single-module compilation doesn't
buy you a lot in Verilog or SV (unlike VHDL, where compiling
a module successfully is pretty much a guarantee that it can
be elaborated correctly). If your module has an interface-
type port and you compile it, there is no check that the
interface has the form that your code expects. See my recent
rant-paper at DVCon for further evidence of how this stuff
rather easily raises my blood pressure.
--
Jonathan Bromley, Consultant

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