Synthesis Quesiton (single module vs. multiple modules)

[thomasc]

Hi,

I have a question regarding synthesizing a verilog project.
Let's say we have 5 modules in a project and want to synthesize them. My
question is that if there's any difference between "placing all 5 modules
in a single .v file" and "having five .v files so each file consists of
one module".

Is there any difference between the two methods? (such as number of
modules created, P & R or timing)
Thanks!

[j***@gmail.com]

If you are using ungroup -all in ur script. then it doesnt make a
difference.

logic optmisations will not cross module boundary unless ungroup
command is used. also pin(hierachical) names will be preserved in
Netlist.

[Neo]

You saving in terms of resources will be meagre but then you will be
sacrificing the modularity of the design.