Xilinx, VHDL, Verilog, ModelSim, BMP

[Jim Wu]

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.

HTH,
Jim
***@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



module wr_bin ();

reg [7:0] data;

integer fd;
integer i;

initial begin
fd = $fopen("test.bin", "wb");

for (i = 0; i < 256; i = i + 1) begin
data = i;

if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end

$fclose(fd);
$display("Done");
$finish;
end

endmodule

[Jim Wu]

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.

HTH,
Jim
***@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



module wr_bin ();

reg [7:0] data;

integer fd;
integer i;

initial begin
fd = $fopen("test.bin", "wb");

for (i = 0; i < 256; i = i + 1) begin
data = i;

if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end

$fclose(fd);
$display("Done");
$finish;
end

endmodule

[Eric Crabill]

Dude, you rock!!! Since I'm using Modelsim at home
for my hobby projects, this will work fantastic...
Now I can write out TIFF files direct from Verilog.

Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...

My desire is to have a loop, that writes each display
frame to a separate file, with names like:

frame01.tif
frame02.tif
frame03.tif
frame04.tif
and so on...

Thanks, I appreciate your help,
Eric

Post by Jim Wu

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.
HTH,
Jim
http://www.geocities.com/jimwu88/chips
module wr_bin ();
reg [7:0] data;
integer fd;
integer i;
initial begin
fd = $fopen("test.bin", "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
$display("Done");
$finish;
end
endmodule

[John Williams]

Hi Eric,

Post by Eric Crabill
Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...

I know it can be done in VHDL, but not sure about Verilog sorry.

I can dig out the details if you're interested.

John

[Eric Crabill]

Hi,

Jim posted some stuff that looks like it will solve
my problem. I'm going to work on my TIFF writer over
the weekend and when I'm done (and if it works...)
I will post it here.

Thanks,
Eric

Post by John Williams
Hi Eric,

Post by Eric Crabill
Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...

I know it can be done in VHDL, but not sure about Verilog sorry.
I can dig out the details if you're interested.
John

[Jim Wu]

A typo, fn should have been defined as "reg [10*8:1] fn;".

Post by Jim Wu
module wr_bin ();
reg [7:0] data;
reg [10*8:0] fn;
reg [7:0] seq;
integer fd;
integer i, j;
initial begin
for (j = 0; j < 8; j = j + 1) begin
seq = 8'h30 + j;
fn = {"frame", seq, ".tif"};
fd = $fopen(fn, "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
end
$display("Done");
$finish;
end
HTH,
Jim
http://www.geocities.com/jimwu88/chips

Post by Eric Crabill
Dude, you rock!!! Since I'm using Modelsim at home
for my hobby projects, this will work fantastic...
Now I can write out TIFF files direct from Verilog.
Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...
My desire is to have a loop, that writes each display
frame01.tif
frame02.tif
frame03.tif
frame04.tif
and so on...
Thanks, I appreciate your help,
Eric

Post by Jim Wu

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.
HTH,
Jim
http://www.geocities.com/jimwu88/chips
module wr_bin ();
reg [7:0] data;
integer fd;
integer i;
initial begin
fd = $fopen("test.bin", "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
$display("Done");
$finish;
end
endmodule

[Eric Crabill]

Thanks, I am going to try integrating this into my
existing TIFF file writer and I'll let you know
how it works out for me. I really appreciate the
thought you put into it.

Eric

Post by Jim Wu
A typo, fn should have been defined as "reg [10*8:1] fn;".

Post by Jim Wu
module wr_bin ();
reg [7:0] data;
reg [10*8:0] fn;
reg [7:0] seq;
integer fd;
integer i, j;
initial begin
for (j = 0; j < 8; j = j + 1) begin
seq = 8'h30 + j;
fn = {"frame", seq, ".tif"};
fd = $fopen(fn, "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
end
$display("Done");
$finish;
end
HTH,
Jim
http://www.geocities.com/jimwu88/chips

Post by Eric Crabill
Dude, you rock!!! Since I'm using Modelsim at home
for my hobby projects, this will work fantastic...
Now I can write out TIFF files direct from Verilog.
Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...
My desire is to have a loop, that writes each display
frame01.tif
frame02.tif
frame03.tif
frame04.tif
and so on...
Thanks, I appreciate your help,
Eric

Post by Jim Wu

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.
HTH,
Jim
http://www.geocities.com/jimwu88/chips
module wr_bin ();
reg [7:0] data;
integer fd;
integer i;
initial begin
fd = $fopen("test.bin", "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
$display("Done");
$finish;
end
endmodule

[Jim Wu]

You're welcome.

I didn't try this myself, but theoretically it should work: if you need
"seq" to be more than 1 digit, you can try swrite* tasks.

Jim

Post by Eric Crabill
Thanks, I am going to try integrating this into my
existing TIFF file writer and I'll let you know
how it works out for me. I really appreciate the
thought you put into it.
Eric

Post by Jim Wu
A typo, fn should have been defined as "reg [10*8:1] fn;".

Post by Jim Wu
module wr_bin ();
reg [7:0] data;
reg [10*8:0] fn;
reg [7:0] seq;
integer fd;
integer i, j;
initial begin
for (j = 0; j < 8; j = j + 1) begin
seq = 8'h30 + j;
fn = {"frame", seq, ".tif"};
fd = $fopen(fn, "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
end
$display("Done");
$finish;
end
HTH,
Jim
http://www.geocities.com/jimwu88/chips

Post by Eric Crabill
Dude, you rock!!! Since I'm using Modelsim at home
for my hobby projects, this will work fantastic...
Now I can write out TIFF files direct from Verilog.
Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...
My desire is to have a loop, that writes each display
frame01.tif
frame02.tif
frame03.tif
frame04.tif
and so on...
Thanks, I appreciate your help,
Eric

Post by Jim Wu

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.
HTH,
Jim
http://www.geocities.com/jimwu88/chips
module wr_bin ();
reg [7:0] data;
integer fd;
integer i;
initial begin
fd = $fopen("test.bin", "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
$display("Done");
$finish;
end
endmodule

[Jim Wu]

Try this (tested in mti 5.8e):

module wr_bin ();

reg [7:0] data;
reg [10*8:0] fn;
reg [7:0] seq;

integer fd;
integer i, j;

initial begin

for (j = 0; j < 8; j = j + 1) begin
seq = 8'h30 + j;
fn = {"frame", seq, ".tif"};
fd = $fopen(fn, "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;

if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end


$fclose(fd);
end

$display("Done");
$finish;
end

HTH,
Jim
***@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

Post by Eric Crabill
Dude, you rock!!! Since I'm using Modelsim at home
for my hobby projects, this will work fantastic...
Now I can write out TIFF files direct from Verilog.
Let me ask another question, if you don't mind. Do
you (or anyone reading) know if it's possible to
open files with dynamic file names? By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name? I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...
My desire is to have a loop, that writes each display
frame01.tif
frame02.tif
frame03.tif
frame04.tif
and so on...
Thanks, I appreciate your help,
Eric

Post by Jim Wu

Hi,
Well, let me know if you figure this one out. I had
a similar issue -- I wanted a Verilog simulation to
write out a TIFF file. I couldn't find a way to write
out a binary file, so wrote out ASCII data values to
text file and then post-processed it into a binary
TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.
HTH,
Jim
http://www.geocities.com/jimwu88/chips
module wr_bin ();
reg [7:0] data;
integer fd;
integer i;
initial begin
fd = $fopen("test.bin", "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
$display("Done");
$finish;
end
endmodule

[Steven Sharp]

Post by Jim Wu
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);

Shouldn't that be $fseek(fd, -3, 1), to seek backwards
3 bytes from the current position to compensate for
having written a 4-byte binary word instead of 1 byte?
With $fseek(fd, 1, 0), you are seeking to the second
byte in the file, which is only correct if you were
at the start of the file when you wrote the NUL byte.

Some simulators actually let you write a NUL byte
out with %c, which avoids this nastiness.

[Jim Wu]

Post by Steven Sharp

Post by Jim Wu
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);

Shouldn't that be $fseek(fd, -3, 1), to seek backwards
3 bytes from the current position to compensate for
having written a 4-byte binary word instead of 1 byte?
With $fseek(fd, 1, 0), you are seeking to the second
byte in the file, which is only correct if you were
at the start of the file when you wrote the NUL byte.

You are absolutely right. My first posting was to show how to get around the
problem that some simulators (e.g. Modelsim) cannot write out the NULL byte.
Of course a more general solution is using $fseek(fd, -3, 1) as you pointed
out.

Post by Steven Sharp
Some simulators actually let you write a NUL byte
out with %c, which avoids this nastiness.

I know NCVerilog can do this, but not all simulators work this way.

Jim

[Eric Crabill]

Hi,

task WRITE_BYTE;
input [7:0] data;
integer position;
begin
if (data == 0)
begin
position = $ftell(file_ptr);
position = position + 1;
$fwriteb(file_ptr, "%u", data);
$fseek(file_ptr, position, 0);
end
else
begin
$fwriteb(file_ptr, "%c", data);
end
end
endtask

Are you saying that a more concise way to do
this would be with a relative seek? I don't
have a good reference for these system tasks,
the best I could come up with is what I put
above, based on reading some web material.

$fseek(fd, -3, 1)

Seems much more concise... It's equivalent?
Eric

[Steven Sharp]

Post by Eric Crabill
Are you saying that a more concise way to do
this would be with a relative seek? I don't
have a good reference for these system tasks,
the best I could come up with is what I put
above, based on reading some web material.

What you came up with should work. It even has
the advantage of being clearer in some ways, and
doesn't rely on the implementation correctly
following the LRM in writing out 32-bit chunks
with %u. But a relative seek is more concise.
The third argument to $fseek is 0 for a seek
relative to the start of the file, 1 for a seek
relative to the current position in the file,
and 2 for a seek relative to the end of the file.
This assumes that your simulator has implemented
$fseek correctly, of course.

Post by Eric Crabill

Post by Steven Sharp
$fseek(fd, -3, 1)

Seems much more concise... It's equivalent?

Should be.

[Eric Crabill]

Hi,

Sorry it took so long, but here it is,
a module that will record RGB video
data to TIFF files. A small testbench
is also provided:

http://www.fpga-games.com/cx2600/tiff/

I hope it helps somebody, I found it
useful. I'd like to thank everyone
for their input on this topic.

Eric

[Steven Sharp]

Post by Jim Wu

Post by Steven Sharp
Some simulators actually let you write a NUL byte
out with %c, which avoids this nastiness.

I know NCVerilog can do this, but not all simulators work this way.

NC-Verilog didn't work this way originally either. We added this
capability in response to user requests. Perhaps other simulator
vendors would also be willong to do this if they got enough requests.

In the meantime, the basic workaround you suggested should work.