How to display upcase char in verilog?

[Ensoul Chee]

I have a 32bit reg.
Now I want to display the value of it on screen or write to file with
upcase char.
How could I do it?

such as reg [31:00] test_vector = 32'habcd_abcd;

I use $display (test_vector); then I got "abcdabcd" But I hope the
output is "ABCDABCD"

How can I do it in verilog?


Thanks in Advance

[Steven Sharp]

Post by Ensoul Chee
I have a 32bit reg.
Now I want to display the value of it on screen or write to file with
upcase char.
How could I do it?

There is no way of doing this using $display. You could write your
own Verilog code to print a value in hexadecimal. It would have to
have a loop that takes each set of 4 bits and converts it into a hex
output character (using a case statement or indexing into an array of
characters). Then you can produce upper case or whatever you like.
I don't know why this would be important enough to bother, though.

[Ensoul Chee]

Post by Steven Sharp

Post by Ensoul Chee
I have a 32bit reg.
Now I want to display the value of it on screen or write to file with
upcase char.
How could I do it?

There is no way of doing this using $display. You could write your
own Verilog code to print a value in hexadecimal. It would have to
have a loop that takes each set of 4 bits and converts it into a hex
output character (using a case statement or indexing into an array of
characters). Then you can produce upper case or whatever you like.
I don't know why this would be important enough to bother, though.

Anyway thanks for you reply, I think I should try to find other ways to
finish it.

[Francisco Camarero]

The same way this C program:

int main() {

long int test_vector = 0xabcdabcd;

printf ("%d, %x, %X\n",test_vector,test_vector,test_vector);

}

prints out:

-1412584499, abcdabcd, ABCDABCD


And after reading QUALIS Verilog HDL Quick Reference Card, that
defines %h/%H instead of %x/%X for hexadecimal, I have tried the
verilog code:

module test;

reg [31:00] test_vector ;

initial
begin
test_vector = 32'habcdabcd;

$display ("%d, %h, %H",test_vector,test_vector,test_vector);

end

endmodule

only to get:

2882382797, abcdabcd, abcdabcd

with both the mainstream Verilog simulators in the market...

Any comment from the simulator producers ?

Fran.

Post by Ensoul Chee
I have a 32bit reg.
Now I want to display the value of it on screen or write to file with
upcase char.
How could I do it?
such as reg [31:00] test_vector = 32'habcd_abcd;
I use $display (test_vector); then I got "abcdabcd" But I hope the
output is "ABCDABCD"
How can I do it in verilog?
Thanks in Advance

[Steven Sharp]

Post by Francisco Camarero
-1412584499, abcdabcd, ABCDABCD
2882382797, abcdabcd, abcdabcd
with both the mainstream Verilog simulators in the market...

In other words, you are proposing something as a solution that
you already know doesn't work.

Post by Francisco Camarero
Any comment from the simulator producers ?

The Verilog language is not the C language. It is defined by the
Verilog language standard, not the C language standard. The fact
that there are some similarities does not mean that they behave
the same way in all respects.

The behavior of Verilog was effectively defined by Verilog-XL.
This already defined %H to be equivalent to %h, probably well
before %X was added to the ISO C standard with a different meaning
from %x.

[Srinivasan Venkataramanan]

Hi,
Based on ASCII representation one could write a function to convert
LOWER Case to UPPER Case, but since Verilog doesn't have attributes
(as in VHDL) I am not sure if there is an easy way to make a generic
to_upper function that would work over varying reg sizes. Here is a
piece of code to convert 1 char - could easily be modified to fit 32
bit.

HTH,
Srinivasan
http://www.noveldv.com

module upcase ();
reg [7:0] char;
initial
begin
char = "a";
$monitor ("%d %C ", to_upper(char), to_upper(char));
end
function [7:0] to_upper (input [7:0] in_char);
begin
to_upper = in_char;
if (in_char > 96)
to_upper = in_char - 32;
end
endfunction // to_upper
endmodule

Post by Ensoul Chee
I have a 32bit reg.
Now I want to display the value of it on screen or write to file with
upcase char.
How could I do it?
such as reg [31:00] test_vector = 32'habcd_abcd;
I use $display (test_vector); then I got "abcdabcd" But I hope the
output is "ABCDABCD"
How can I do it in verilog?
Thanks in Advance