vcd file

[Vandana]

Hello All,

Is there a way to determine the input/outputs of a module from a
vcd file?

Can I use the $dumpports command for this? How do I make $dumpports
look for all modules instantiated below the top level module. I am
using VCS, verilog.

Thanks for your help.

Vandana.

[Vandana]

I want the VCD for only input/outputs for all modules in the design.
Is there a way to do this?
If not, is there a way to figure out from the VCD, which signals are
inputs and outputs for a module?

Thanks,

Post by Vandana
Hello All,
   Is there a way to determine the input/outputs of a module from a
vcd file?
Can I use the $dumpports command for this? How  do I make $dumpports
look for all modules instantiated below the top level module.  I am
using VCS, verilog.
Thanks for your help.
Vandana.

[Petter Gustad]

Post by Vandana
Is there a way to determine the input/outputs of a module from a
vcd file?

Not in a standard VCD file. That's why most vendors use some other
form of dump file like SST, TRN, VPD, VCD+ etc. to record information
about data types, inputs, outputs, assertions, etc.

Petter

[Vandana]

Thanks for your response. I have a doubt regarding the VCD file.

Reading the IEEE std for verilog, I understand that $dumpvars
lists initial values of all variables that are dumped.

So doesn't this mean that in the section $dumpvars in the VCD file, I
should see the
initial values of all variables? But I dont see the initial values for
all variables.
Have I done something worng that I am not able to see initial values
for all variables?

Can someone please clarify this.

Thanks.

Post by Petter Gustad

Post by Vandana
   Is there a way to determine the input/outputs of a module from a
vcd file?

Not in a standard VCD file. That's why most vendors use some other
form of dump file like SST, TRN, VPD, VCD+ etc. to record information
about data types, inputs, outputs, assertions, etc.
Petter
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.sig removed by request.