news.singnet.com.sg
2007-11-29 15:38:37 UTC
Basically my design employees 16 pieces of 32-bit registers,
reg [31:0] temp_mem[0:15];
During writing to the memory, fine, I put it in a always @(clock)..
statement.
However during reading, I need it to be in a combinational circuit.
always @(temp_mem or read1 or read2 or read3 ...)
In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.
The reading is too complicated for a simple assign statement.
Any solutions?
reg [31:0] temp_mem[0:15];
During writing to the memory, fine, I put it in a always @(clock)..
statement.
However during reading, I need it to be in a combinational circuit.
always @(temp_mem or read1 or read2 or read3 ...)
In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.
The reading is too complicated for a simple assign statement.
Any solutions?