Clock multiplier

[Neil]

I am looking for a simple synthesizable clock multiplier verilog code
which can multiply the clock input by 2 OR 4 (clk*2 OR clk*4)
Thanks
Neil

[Jason Zheng]

Post by Neil
I am looking for a simple synthesizable clock multiplier verilog code
which can multiply the clock input by 2 OR 4 (clk*2 OR clk*4)
Thanks
Neil

There is no simple verilog code that accomplish that. If you are using
xilinx products, try using their DLL modules.

[z***@yahoo.com]

Actually while writing a code we assume a basic frequency signal which
toggles the other logic. so you cannot write a code to generate a
higher frequency signal from a lower one.
You have to do it in physical domain as expressed above.

[Nils Strandberg]

Post by Neil
I am looking for a simple synthesizable clock multiplier verilog code
which can multiply the clock input by 2 OR 4 (clk*2 OR clk*4)
Thanks
Neil

No really easy way, look at the specification of your device. Most of
the bigger have DLLs. if your have, use it.

Way back, when no devices had DLLs, we used a rather crude trick. You
feed the clock to one toggling DFF and also to another DFF via a lot of
instantiated inverters/buffers (to get a lot of delay). XOR the outputs
and you will get a pulse at the clock edge (the width will be the amount
of delay you have been able to introduce). Then we made another copy of
the logic, but with an inverted clock. XORing together the resulting
signals gave a short pulse at both rising and falling clock edge.

That meant we had actually doubled the clock frequency, but usually it
was of little use, since the clock was not nearly symmetrical. The fix
for that was to do it all over again and divide the resulting clock by
two to get it symmetrical.

Worked only for relatively slow clocks since the process used had to be
able to cope with twice the frequency we needed.

I do not recommend you to try this, it is just that I have filed it
under the tab "meaningless knowledge" and I do not seem to be able to
scrub it (the tab) completeatly clean. But, if you can not find another
help you can try it.

When we used it, synthesis tools where not so advanced so they usually
did what they where told. Nowadays I guess it would be a lot of problems
(if possible) to get any of them not to optimize away the extra delay
introduced.

/NS

[Neil]

Then we made another copy of the logic, but with an inverted clock.

XORing together >> the resulting signals gave a short pulse at both
rising and falling clock edge.

Why do we need this ? If we successfyllu introduce a delay equalent to
1/4th the clock period of original clock, we would have the 2x clock
right ?

In case of a 100 MHz Clock (clk), is this the behavioral model of what
we are doing ? Why do we need the inverted clock logic ?

clk_delay <= #2.5 clk;
clk2x <= clk xor clk_delay.

BTW, the idea is really wonderful and thanks alot for sharing valuable
knowledge !

- Neil

[John_H]

Please note that the delay element (#2.5) is NOT SYNTHESIZABLE !!!

You don't have anything in your silicon to give you predefined delays
without a significant amount of work and/or other reference-based delays
such as DLLs or PLLs.

Because we can't synthesize #2.5, we cannot get a clock multiplier without a
DLL, PLL, or delays we can count on.

Post by Neil

Then we made another copy of the logic, but with an inverted clock.

XORing together >> the resulting signals gave a short pulse at both
rising and falling clock edge.
Why do we need this ? If we successfyllu introduce a delay equalent to
1/4th the clock period of original clock, we would have the 2x clock
right ?
In case of a 100 MHz Clock (clk), is this the behavioral model of what
we are doing ? Why do we need the inverted clock logic ?
clk_delay <= #2.5 clk;
clk2x <= clk xor clk_delay.
BTW, the idea is really wonderful and thanks alot for sharing valuable
knowledge !
- Neil

[Neil]

++++++++++++++++++++++
Then we made another copy of the logic, but with an inverted clock.
XORing together the resulting signals gave a short pulse at both rising
and falling clock edge
++++++++++++++++++++++

Why do we need this ? If we successfully delay the clock the by 1/4th
its time period and xor both the original and delayed clock we get
clk2x right. I know I am thinking in behavioral terms here and it is
not as easy in real case, can you please let me know why you have to
inverth the clocks ?

BTW, The ideal was pretty cool, thanks for sharing the knowledge.
Thanks
Niel

[Georgi Beloev]

Post by Nils Strandberg

Post by Neil
I am looking for a simple synthesizable clock multiplier verilog code
which can multiply the clock input by 2 OR 4 (clk*2 OR clk*4)
Thanks
Neil

No really easy way, look at the specification of your device. Most of
the bigger have DLLs. if your have, use it.
Way back, when no devices had DLLs, we used a rather crude trick. You
feed the clock to one toggling DFF and also to another DFF via a lot of
instantiated inverters/buffers (to get a lot of delay). XOR the outputs
and you will get a pulse at the clock edge (the width will be the amount
of delay you have been able to introduce). Then we made another copy of
the logic, but with an inverted clock. XORing together the resulting
signals gave a short pulse at both rising and falling clock edge.
That meant we had actually doubled the clock frequency, but usually it
was of little use, since the clock was not nearly symmetrical. The fix
for that was to do it all over again and divide the resulting clock by
two to get it symmetrical.
Worked only for relatively slow clocks since the process used had to be
able to cope with twice the frequency we needed.
I do not recommend you to try this, it is just that I have filed it
under the tab "meaningless knowledge" and I do not seem to be able to
scrub it (the tab) completeatly clean. But, if you can not find another
help you can try it.
When we used it, synthesis tools where not so advanced so they usually
did what they where told. Nowadays I guess it would be a lot of problems
(if possible) to get any of them not to optimize away the extra delay
introduced.
/NS

I've used something kind-of similar for a CPLD design. Since simple
delays are optimized away by the synthesis tool I created a flip-flop
toggling on both clock edges. This is accomplished by an xor and looks
like this (hopefully correct, it's been a while):

input clk;
output clk2;
reg ff;

assign clk2 = clk ^ ff;

always @(posedge clk2)
ff <= ~ff;

This creates a short pulse on each clk edge.

-- Georgi

[Neil]

Geoigi, I am actually looking to generate a clk2x out of clkx.

- Niel

[Georgi Beloev]

Post by Neil
Geoigi, I am actually looking to generate a clk2x out of clkx.
- Niel

Yes, this is what the code I posted does. I know it's weird but it does
the job. If you run a simulation be sure to include some delay on the
xor or otherwise you will not see it. The delay is not required for
post-P&R simulation.

Regards,
-- Georgi

[Neil]

Ok, I get it now. The clk2x duty cycle depends on the delay through
XOR.

Thanks
Niel

[Nils Strandberg]

Post by Neil
Ok, I get it now. The clk2x duty cycle depends on the delay through
XOR.
Thanks
Niel

I did not see the post you are referring to, but delays differing due to
different processing parameters was generally causing problems.

Thinking about it I did err in my first post in this subject., since I
said synthesis tool did not optimize away what you wrote. Completely
wrong, No such tools existed. No Verilog, no VHDL or any other language
existed. It was shematic input that you used (so not all that big
designs). I don't remember what we converted the netlist to, Tegas maybe?

From the file of useless knoeleage, I still remember you could do
advanced things with very primitive gate arrays. Usually you only had
access to NAND, NOR and INVERTER gates (or AND, OR and INVERTER),
depending on process. And, of cause, some kind of DFF or latch.

If you found you needed a smith trigger input what would you do? There
where no support in the silicon for such a thing, but using the widest
NAND gate and the widest NOR you could actuually build one (using a FSM).

Anybodey that hasn't been there that can figure out how it should be
implemented and why it works?

/NS

[Nils Strandberg]

Post by Nils Strandberg

Post by Neil
Ok, I get it now. The clk2x duty cycle depends on the delay through
XOR.
Thanks
Niel

I did not see the post you are referring to, but delays differing due to
different processing parameters was generally causing problems.
Thinking about it I did err in my first post in this subject., since I
said synthesis tool did not optimize away what you wrote. Completely
wrong, No such tools existed. No Verilog, no VHDL or any other language
existed. It was shematic input that you used (so not all that big
designs). I don't remember what we converted the netlist to, Tegas maybe?
From the file of useless knoeleage, I still remember you could do
advanced things with very primitive gate arrays. Usually you only had
access to NAND, NOR and INVERTER gates (or AND, OR and INVERTER),
depending on process. And, of cause, some kind of DFF or latch.
If you found you needed a smith trigger input what would you do? There
where no support in the silicon for such a thing, but using the widest
NAND gate and the widest NOR you could actuually build one (using a FSM).
Anybodey that hasn't been there that can figure out how it should be
implemented and why it works?
/NS

What I forgot to say is that it was in a c-mose process, don't know how
to do the same trick in another (fx bipolar) process.

/NS

[Neil]

Georgi, I am actually looking to generate a clk2x out of clkx.

- Niel