Post by RSGUPTAThere are commands in Icarus tool for compiling verilog
iverilog -c rtl\\files.txt
which compiles the verilog files to a.out file
I guess "files.txt" contains a list of the Verilog files
you want to compile? That's known as a "response file"
or "gather file". In most commercial Verilog compilers
you can use such a file with the -f compiler switch:
vlog -f files.txt # for Mentor simulators
But first you must have created a working library,
or else the vlog command will complain. So the correct
sequence is:
vlib work # do this the first time, once only
vlog -f files.txt # compile all the files
Post by RSGUPTAand then finally the command vvp a.out is used to simulate and view
the waveform in waveform viewver.
Now you need to know the name of the top-level module(s) in
your simulation, so you can do...
vsim top_module_name
Post by RSGUPTAIf the same operation is to be done in Questasim what are the
equivalent commands??
You may find it easier to use the one-shot command
qverilog -gui -f files.txt
which automatically builds a library, compiles everything
in your file list, works out which are the top-level modules
and simulates them. Similar commands exist for other
mainstream simulators; these happen to spring to mind:
irun -gui -f files.txt # Cadence Incisive
vcs -R -f files.txt # Synopsys VCS
And guess what, it's usually all in the documentation.
Though I agree that it's often easier to ask someone
who's done it before, just to get started.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
***@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.