What's the easiest way to bit-wisely reverse a vector?

[Mr. Ken]

I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)

For example,
reg [31:0] mydata;
wire [31:0] mydata_r;

assign mydata_r = mydata[0:31] // Syntax error here.

TIA

[John_H]

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA

Use a Verilog2001 generate for loop to assign each bit of mydata to
mydata_r one at a time. The generate stays pretty compact.

[Mr. Ken]

Post by John_H

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA

Use a Verilog2001 generate for loop to assign each bit of mydata to
mydata_r one at a time. The generate stays pretty compact.

for loop is nice, but anything more compact? maybe I am expecting too much.
:)

[Mr. Ken]

Post by Mr. Ken

Post by John_H

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA

Use a Verilog2001 generate for loop to assign each bit of mydata to
mydata_r one at a time. The generate stays pretty compact.

for loop is nice, but anything more compact? maybe I am expecting too much.

basically a for loop doesn't do well with "assign".

[n***@gmail.com]

A "generate for" loop is different from a "for" loop, whereby the
former is not seen during run-time, much like a compiler directive,
hence wouldn't be causing much problems with assign here ...

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Post by Mr. Ken

Post by Mr. Ken

Post by John_H

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA

Use a Verilog2001 generate for loop to assign each bit of mydata to
mydata_r one at a time. The generate stays pretty compact.

for loop is nice, but anything more compact? maybe I am expecting too

much.
basically a for loop doesn't do well with "assign".

[John_H]

Post by Mr. Ken

Post by Mr. Ken

Post by John_H

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA

Use a Verilog2001 generate for loop to assign each bit of mydata to
mydata_r one at a time. The generate stays pretty compact.

for loop is nice, but anything more compact? maybe I am expecting too

much.
basically a for loop doesn't do well with "assign".

That's why one uses the Verilog 2001 "generate" for statement. It's not
your grandfather's for statement.

Bottom line: the Verilog language has strict vector bit order. If you
declare the elements as increasing (e.g., my[0:35]) then the references
all need to be increasing. I'd *love* to be able to swap back & forth,
reversing the bit order to take care of my too-frequent bit-swizzle
needs but a short generate for statement or a fully expanded vector
assignment is the only way I've found to go.

I'll post the syntax of the generate block when I get in to work.

[John_H]

Post by John_H
Bottom line: the Verilog language has strict vector bit order. If you
declare the elements as increasing (e.g., my[0:35]) then the references
all need to be increasing. I'd *love* to be able to swap back & forth,
reversing the bit order to take care of my too-frequent bit-swizzle needs
but a short generate for statement or a fully expanded vector assignment
is the only way I've found to go.
I'll post the syntax of the generate block when I get in to work.

genvar i;
generate
for( i=0; i<8; i=i+1 )
begin : swiz
assign Y[i] = A[7-i];
end
endgenerate

[Stephen Williams]

Post by John_H

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA

Use a Verilog2001 generate for loop to assign each bit of mydata to
mydata_r one at a time. The generate stays pretty compact.

Something like this:

genvar i;
for (i=0; i<32; i=i+1) assign mydata_r[i] = mydata[31-i];

(The generate/endgenerate is optional because it is obvious to the
parser that this is a generate loop.)

So it's 2 lines instead of 1. Sorry:-)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

[John_H]

I didn't know the Verilog2001 LRM allowed the generate to be optional.
SynplifyPro certainly doesn't like the "obvious" generate block without an
explicit generate/endgenerate. Even the for block needed a name.

Post by Stephen Williams
genvar i;
for (i=0; i<32; i=i+1) assign mydata_r[i] = mydata[31-i];
(The generate/endgenerate is optional because it is obvious to the
parser that this is a generate loop.)
So it's 2 lines instead of 1. Sorry:-)
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

[Stephen Williams]

Post by John_H
I didn't know the Verilog2001 LRM allowed the generate to be optional.
SynplifyPro certainly doesn't like the "obvious" generate block without an
explicit generate/endgenerate. Even the for block needed a name.

The for-loop statement most definitely does *not* need a name. There
is a whole elaborate rule for assigning scope names to generate
blocks that are anonymous is the source code.

As for the generate/endgenerate being optional, I may have gotten
ahead of myself on that one. In fact, I somehow got it in my head
that it is optional (I think I read it in an errata draft) but I
cannot find any definitive reference.

The generate/endgenerate keywords are in fact silly because any
module items (not just generate schemes) are allowed withing them,
so they convey almost no information. Steve Sharp may speak more
authoritatively on this matter (as he often does).

In any case, Icarus Verilog doesn't require generate/endgenerate,
other then to require that generate has a matching endgenerate;-)

Post by John_H

Post by Stephen Williams
genvar i;
for (i=0; i<32; i=i+1) assign mydata_r[i] = mydata[31-i];
(The generate/endgenerate is optional because it is obvious to the
parser that this is a generate loop.)
So it's 2 lines instead of 1. Sorry:-)
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

[Jonathan Bromley]

On Fri, 21 Apr 2006 11:02:14 -0700, Stephen Williams

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Post by John_H
I didn't know the Verilog2001 LRM allowed the generate to be optional.

It doesn't. I think you'll find "generate" became optional
in 1364-2005.

The for-loop statement most definitely does *not* need a name.

Really? Again, I think this is a 1364-2005 relaxation. I'm sure
1364-2001 requires generate-for loop body to be a
labelled begin..end

The generate/endgenerate keywords are in fact silly because any
module items (not just generate schemes) are allowed withing them,
so they convey almost no information. Steve Sharp may speak more
authoritatively on this matter (as he often does).

Interestingly, though, the relaxation makes it much harder for a
compiler to issue clear diagnostics for certain simple errors,
since a for-loop might now be a generate-loop or simply a
procedural loop written by someone who innocently
forgot the preceding "initial" keyword.
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

[Stephen Williams]

Post by Jonathan Bromley
On Fri, 21 Apr 2006 11:02:14 -0700, Stephen Williams

Post by Stephen Williams

Post by John_H
I didn't know the Verilog2001 LRM allowed the generate to be optional.

It doesn't. I think you'll find "generate" became optional
in 1364-2005.

Post by Stephen Williams
The for-loop statement most definitely does *not* need a name.

Really? Again, I think this is a 1364-2005 relaxation. I'm sure
1364-2001 requires generate-for loop body to be a
labelled begin..end

*sigh* I can't refute you. In Icarus Verilog I implemented it
the "-2005" way because I've been working from some drafts of the
newer generate syntax. So it seems that I'm farther ahead of myself
then I originally thought:-O

I think I need to buy myself a copy of the 1364-2005 standard.

[s***@cadence.com]

Some of the changes to generates were intended as corrections to
Verilog-2001, because of significant problems with what was specified
there. After approving the changes, the BTF recommended that
implementations of Verilog-2001 use the revised version. So they could
be considered to be part of a revised Verilog-2001, though there was no
official corrigendum.

Making generate/endgenerate optional was not a necessary correction, so
that could be considered a Verilog-2005 enhancement instead. But there
is not a clear dividing line.

Specifying that conditional generates created scopes was necessary for
practical implementation. Allowing implicit names for those scopes was
necessary to avoid annoyance to users (and to give backward
compatibility with any attempted implementations of the original
specification). But once the implicit naming scheme was added for
conditional generates, there was no reason to continue to require
explicit names for the for-generated scopes. So that change could be
viewed as part of the corrections or as a separate enhancement.

[Stephen Williams]

Post by s***@cadence.com
Some of the changes to generates were intended as corrections to
Verilog-2001, because of significant problems with what was specified
there. After approving the changes, the BTF recommended that
implementations of Verilog-2001 use the revised version. So they could
be considered to be part of a revised Verilog-2001, though there was no
official corrigendum.

So with all that said, I might as well leave Icarus Verilog with
the 2005 behavior because it is almost 2001+ behavior anyhow. And
besides, it's a superset so strictly-2001 programs will care.

And my two-line solution that started this whole thread remains
as valid code if you have a newer compiler.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

[t***@hotmail.com]

If you want to reverse at the chip's top interface, this works:
module m(
input [31:0] a,
output [31:0] b);
assign b=a;
endmodule
// To this
module m(
input [0:31] a,
output [31:0] b);
assign b=a;
endmodule

T

Post by Mr. Ken
I need to reverse the vector, and prefer simplest codes. One liner is
probably the best. :)
For example,
reg [31:0] mydata;
wire [31:0] mydata_r;
assign mydata_r = mydata[0:31] // Syntax error here.
TIA