Initializing Array from String

[Uwe Bonnes]

Hello,

is there an easier way to initialize an verilog array of registers with the
values from a string define.

At least the way I do it below compiles in cver and icarus:

`define CNT_RST_COOKIE "CNT_RST"
module test();

reg [7:0] rst_cookie[0:6];

reg [55:0] string;

integer i, j;
initial
begin
string = `CNT_RST_COOKIE;
for (i=0; i < 7; i = i+1)
begin
rst_cookie[i] = 8'h0;
for (j=0; j<8; j = j+1)
rst_cookie[i] =rst_cookie[i] <<1 |string[8*(i+i)-1+j];
end
end
endmodule // test

Thanks

[Jonathan Bromley]

On Fri, 2 Mar 2007 14:44:33 +0000 (UTC), Uwe Bonnes

Post by Uwe Bonnes
is there an easier way to initialize an verilog array of registers with the
values from a string define.

Unless you use SystemVerilog, I'm not aware of a much
better way; but you definitely make life easier by copying
bytes at a time, not bits!!!

There are a couple of other things you can do to tidy it up:

(1) use parameters somewhat (although that's hard, since you
can't determine the length of a string constant);
(2) make the loop counters local to your begin...end block;
(3) use Verilog-2001 indexed part selects for the vector slicing;
(4) make the string's range ascending to simplify
left-to-right subscripting.


`define CNT_RST_COOKIE "CNT_RST"
`define N_CHARS (7)
module test();

reg [7:0] rst_cookie[0:`N_CHARS-1];

reg [0:(8*`N_CHARS)-1] str; // not 'string'!!!!!
// it's a SystemVerilog keyword, best avoided
initial begin : str_copy
integer i;
string = `CNT_RST_COOKIE;
for (i=0; i < `N_CHARS; i = i+1)
rst_cookie[i] = string[8*i +: 8];
end

endmodule // test

If your "string" is indexed 55:0 then the last line of
code would have to be rewritten:

rst_cookie[i] = string [8*(`N_CHARS-i) - 1 -: 8];

or something similar.
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[Jonathan Bromley]

Post by Jonathan Bromley
reg [0:(8*`N_CHARS)-1] str; // not 'string'!!!!!
// it's a SystemVerilog keyword, best avoided

Yes, I was right about that. It's a pity I then forgot to
edit the variable name in the rest of the code....

Post by Jonathan Bromley
string = `CNT_RST_COOKIE;

that'll be
str = `CNT_RST_COOKIE;

Post by Jonathan Bromley
rst_cookie[i] = string[8*i +: 8];

and again:
rst_cookie[i] = str[8*i +: 8];

Apologies for any confusion.
--
Jonathan Bromley, Consultant

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[Uwe Bonnes]

Post by Jonathan Bromley
On Fri, 2 Mar 2007 14:44:33 +0000 (UTC), Uwe Bonnes

Post by Uwe Bonnes
is there an easier way to initialize an verilog array of registers with the
values from a string define.

Unless you use SystemVerilog, I'm not aware of a much
better way; but you definitely make life easier by copying
bytes at a time, not bits!!!
(1) use parameters somewhat (although that's hard, since you
can't determine the length of a string constant);
(2) make the loop counters local to your begin...end block;

Good hint

Post by Jonathan Bromley
(3) use Verilog-2001 indexed part selects for the vector slicing;

At least in ten way I coded it, neither cver not iverilog allowed
me to use bit-range selects in the for loop
...

Post by Jonathan Bromley
rst_cookie[i] = string[8*i +: 8];

^^
Any pointer where this syntax is explained?

Thanks

[Jonathan Bromley]

On Sat, 3 Mar 2007 01:59:36 +0000 (UTC), Uwe Bonnes

Post by Uwe Bonnes

Post by Jonathan Bromley
(3) use Verilog-2001 indexed part selects for the vector slicing;

At least in ten way I coded it, neither cver not iverilog allowed
me to use bit-range selects in the for loop

No; you can't use [start:end] syntax unless "start" and "end" are
both constants (unlike VHDL). But the "indexed part select" syntax,
using +: or -:, was added to deal with exactly this sort of problem.

Post by Uwe Bonnes
Any pointer where this [start +: width] syntax is explained?

It's Verilog-2001; explained in detail in the 1364-2001 or 1364-2005
LRM. The idea is simple:

[start_index +: width] or [start_index -: width]

width must be constant, so that Verilog can determine the bit-width
of the expression at compile time; start_index can be any expression.
The only surprising feature is the way this interacts with ascending
and descending subscripts. In the case of +:, the subscripts are
calculated like this:

[start_index +: width] =>
lowest-numbered subscript = start_index
highest_numbered subscript = start_index + width - 1

Now we must arrange the subscripts into the right order,
highest:lowest or lowest:highest, depending on the declaration
of the thing you are subscripting. Verilog does this automatically.
Similarly for -: where lowest-subscript = start_index,
highest-subscript = start_index + 1 - width.

All the commercial tools I use now fully support this, although
for some of them you need to enable V-2001 explicitly; I don't
know about icarus and cver.

Post by Uwe Bonnes
Thanks

You're welcome.

Cheap shameless advertising: Verilog-2001 constructs are fully
catalogued in our Golden Reference Guide
www.doulos.com/content/products/golden_reference_guides.php
--
Jonathan Bromley, Consultant

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[Stephen Williams]

Post by Jonathan Bromley
It's Verilog-2001; explained in detail in the 1364-2001 or 1364-2005
[start_index +: width] or [start_index -: width]

[...]

Post by Jonathan Bromley
All the commercial tools I use now fully support this, although
for some of them you need to enable V-2001 explicitly; I don't
know about icarus and cver.

Icarus Verilog supports it in current snapshots. (I guess the v0.8
stable branch is getting pretty old, but I have specific milestones
I'm trying to reach for the 0.9 release.)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."