Illegal reference to net

[maTheMatic]

HI,all
I am learning verilog. The following codes can't be compiled with
the error information "Illegal reference to net "out"" under the
Modelsim SE.

module connect(
input wire in,
output wire out
);

always
begin
#3 out <= in;
end
endmodule

Why can't I direct assign (or connect directly) the input wire to the
output wire? When I change the type of out from wire to reg,then every
thing is ok. Yes, I know the reg can't be assigned with wire type's
things, but how about wire to wire?what is the basic laws behind the
assignment?

Regards

[Pooja Maheshwari]

Its simple.
Inside always block, you can only assign to reg or variables not nets.
With assign statement, you can assign nets.
In both type of assignments, you can have either wire or reg on RHS.

- Pooja

Post by maTheMatic
HI,all
I am learning verilog. The following codes can't be compiled with
the error information "Illegal reference to net "out"" under the
Modelsim SE.
module connect(
input wire in,
output wire out
);
always
begin
#3 out <= in;
end
endmodule
Why can't I direct assign (or connect directly) the input wire to the
output wire? When I change the type of out from wire to reg,then every
thing is ok. Yes, I know the reg can't be assigned with wire type's
things, but how about wire to wire?what is the basic laws behind the
assignment?
Regards

[Neo]

Post by maTheMatic
HI,all
I am learning verilog. The following codes can't be compiled with
the error information "Illegal reference to net "out"" under the
Modelsim SE.
module connect(
input wire in,
output wire out
);
always
begin
#3 out <= in;
end
endmodule

The rule is you cant assign to a wire inside an always block.

[maTheMatic]

what is the consideration behind the above rule? or where can I find
the reference? thx for both of above guys!

[Swapnajit Mittra]

Post by maTheMatic
what is the consideration behind the above rule? or where can I find
the reference? thx for both of above guys!

Some people will say that a 'wire' type in Verilog
is supposed to be something akin to a physical
wire - that carries a signal but can not store
a value. You will have to use a 'reg' type to do
that.

But, more simply speaking, Verilog being a programming
language, just as all languages, you need to abide by
some rules and regulations. In this case, it is 'a wire
type variable can not be a valid L-value of a procedural
assignment statement'.

Official Verilog Language Reference Manual (IEEE Std.
1364-2001) can be purchased from IEEE store at

http://standards.ieee.org

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